1. Field of the Invention
Embodiments of the present invention generally relate to fabricating and surface mounting integrated circuit packages.
2. Description of the Related Art
Integrated circuit (IC) fabrication is a multi-step sequence which includes processes such as patterning, deposition, etching, and metallization. Typically, in the final processing steps, the resulting IC die are separated and packaged. IC packaging serves several purposes, including providing an electrical interface with the die, providing a thermal medium through which heat may be removed from the die, and/or providing mechanical protection for the die during subsequent usage and handling.
One type of IC packaging technique is referred to as “flip chip” packaging. In flip chip packaging, after the metallization process is complete, solder bump structures (e.g., solder balls, pads, etc.) are deposited on the die, and the die is separated from the wafer (e.g., via dicing, cutting, etc.). The die is then inverted and positioned on a substrate so that the solder bumps align with electrical connections formed on the substrate. Heat is applied via a solder reflow process to re-melt the solder bumps and attach the die to the substrate. The die/substrate assembly may further be underfilled with a non-conductive adhesive to strengthen the mechanical connection between the die and the substrate.
IC fabrication techniques have enabled the production of larger-sized die having higher and higher transistor densities. Consequently, IC packaging techniques have encountered challenges for providing packaging which supports the requisite number of electrical connections. In general, as the size of the die and number of electrical connections to the die is increased, the size of the package is increased. Further, as package size is increased, the thermal properties of the die and packaging materials become a more important factor.
One relevant thermal property of the die and packaging materials is the coefficient of thermal expansion (CTE). In flip chip packaging, for example, during the solder reflow process, the die is attached to the substrate at an elevated temperature. Upon cooling, a mismatch between the CTE of the die and the CTE of the substrate may cause the substrate to warp, reducing the planarity of the IC package and preventing electrical connections from being formed with the IC package. Additionally, warping of the IC package may affect the electrical connections provided between the die and the substrate. Moreover, IC packages which experience significant warping may be discarded for being outside of specification requirements.
Accordingly, there is a need in the art for a more effective way of compensating for a CTE mismatch between an IC die and other components of the IC packaging.